@article{lim:1992,
   author = {Lim, Y. C.},
   title = {Single-precision multiplier with reduced circuit complexity for signal processing applications},
   journal = {Computers, IEEE Transactions on},
   volume = {41},
   number = {10},
   pages = {1333-1336},
   note = {Original Research},
   keywords = {digital arithmetic
multiplying circuits
signal processing
reduced circuit complexity
signal processing applications
single precision multiplier
Complexity theory
Convolution
Encoding
Error analysis
Performance analysis
Polynomials
Systolic arrays
Very large scale integration},
   ISSN = {0018-9340},
   DOI = {10.1109/12.166611},
   url = {http://ieeexplore.ieee.org/ielx1/12/4276/00166611.pdf?tp=&arnumber=166611&isnumber=4276},
   year = {1992},
   type = {Journal Article}
}

@inproceedings{king:1997,
   author = {King, E. J. and Swartzlander, E. E.},
   title = {Data-dependent truncation scheme for parallel multipliers},
   booktitle = {Signals, Systems \& Computers, 1997. Conference Record of the Thirty-First Asilomar Conference on},
   volume = {2},
   pages = {1178-1182 vol.2},
   year = {1997},
   abstract = {The variable correction truncated multiplier is introduced. This is a method for minimizing the error of a truncated multiplier. The error is reduced by using information from the partial product bits of the column adjacent to the truncated LSB. This results in a complexity savings while introducing minimum distortion to the result.},
   keywords = {digital arithmetic
error analysis
multiplying circuits
parallel processing
complexity savings
data-dependent truncation
error minimization
harmonic distortion
partial product bits
signal processing
sine wave analysis
truncated LSB
variable correction truncated multiplier
Computer errors
Computer industry
Distortion
Drives
Energy consumption
Equations
Error correction
Roundoff errors},
   ISBN = {1058-6393},
   DOI = {10.1109/ACSSC.1997.679090},
   url = {http://ieeexplore.ieee.org/ielx4/5559/14886/00679090.pdf?tp=&arnumber=679090&isnumber=14886},
   type = {Conference Proceedings}
}

@article{decaro:2013,
   author = {De Caro, D. and Petra, N. and Strollo, A. G. M. and Tessitore, F. and Napoli, E.},
   title = {Fixed-Width Multipliers and Multipliers-Accumulators With Min-Max Approximation Error},
   journal = {Circuits and Systems I: Regular Papers, IEEE Transactions on},
   volume = {60},
   number = {9},
   pages = {2375-2388},
   keywords = {approximation theory
matrix algebra
minimax techniques
multiplying circuits
MAE
approximation error reduction
compensation function
correction function
elementary function
fixed-width multiplier circuit
fixed-width multiplier topology
fixed-width multiplier-accumulator circuit
function evaluation
hardware computation
hardware cost reduction
maximum absolute error
min-max approximation error
multipliers-accumulator
partial products matrix
piecewise linear approximation
size 65 nm
Approximation error
Equations
Hardware
Integrated circuits
Mean square error methods
Optimization
Digital arithmetic
error analysis
error compensation
fixed-width multipliers
min-max approximation
multiplication},
   ISSN = {1549-8328},
   DOI = {10.1109/TCSI.2013.2245252},
   url = {http://ieeexplore.ieee.org/ielx7/8919/6587116/06469188.pdf?tp=&arnumber=6469188&isnumber=6587116},
   year = {2013},
   type = {Journal Article}
}

@article{verdu:1983,
   author = {Verdu, S. and Poor, H. V.},
   title = {Minimax Robust Discrete-Time Matched Filters},
   journal = {Communications, IEEE Transactions on},
   volume = {31},
   number = {2},
   pages = {208-215},
   abstract = {The problem of designing finite-length discrete-time matched filters is considered for situations in which exact knowledge of the input signal and/or noise characteristics is not available. Such situations arise in many applications due to channel distortion, incoherencies, nonlinear effects, and other modeling uncertainties. In such cases it is often of interest to design a minimax robust matched filter, i.e., a nonadaptive filter with an optimum level of worst-case performance for the expected uncertainty class. This problem is investigated here for three types of uncertainty models for the input signal, namely, the mean-absolute, mean-square, and maximum-absolute distortion classes, and for a wide generality of norm-deviation models for the noise covariance matrix. Some numerical examples illustrate the robustness properties of the proposed designs.},
   keywords = {Discrete-time filters
Matched filters
Minimax optimization
Robust methods
Additive noise
Filtering
Minimax techniques
Noise robustness
Nonlinear distortion
Nonlinear filters
Signal design
Signal to noise ratio
Uncertainty},
   ISSN = {0090-6778},
   DOI = {10.1109/TCOM.1983.1095790},
   url = {http://ieeexplore.ieee.org/ielx5/26/23968/01095790.pdf?tp=&arnumber=1095790&isnumber=23968},
   year = {1983},
   type = {Journal Article}
}

@article{ma:1990,
   author = {Ma, G. K. and Taylor, F. J.},
   title = {Multiplier policies for digital signal processing},
   journal = {ASSP Magazine, IEEE},
   volume = {7},
   number = {1},
   pages = {6-20},
   abstract = {The successful design of digital signal processing (DSP) systems and subsystems is often predicated on realizing fast multiplication in digital hardware. This tutorial provides the reader with a broad perspective of this important field and the pedagogy needed to understand the basic principles of digital multiplication. Both conventional and nonconventional methods of implementing multiplication, representing a mix of speed/complexity tradeoffs, are presented. Some are based on traditional shift-add structures, whereas others strive for greater mathematical sophistication. Topics include stand-alone fixed-point multipliers, cellular arrays, memory intensive policies, homomorphic systems, and modular arithmetic.<<ETX>>},
   keywords = {cellular arrays
computerised signal processing
digital arithmetic
multiplying circuits
digital hardware
digital multiplication
digital signal processing
fast multiplication
homomorphic systems
memory intensive policies
modular arithmetic
shift-add structures
speed/complexity tradeoffs
stand-alone fixed-point multipliers
tutorial
Central Processing Unit
Computer architecture
Costs
Digital signal processing chips
Fixed-point arithmetic
Hardware
Logic devices
Signal design
Very large scale integration},
   ISSN = {0740-7467},
   DOI = {10.1109/53.45968},
   url = {http://ieeexplore.ieee.org/ielx1/53/1737/00045968.pdf?tp=&arnumber=45968&isnumber=1737},
   year = {1990},
   type = {Journal Article}
}

@article{verdu:1984,
   author = {Verdu and x and S. and Poor, H. V.},
   title = {On minimax robustness: A general approach and applications},
   journal = {Information Theory, IEEE Transactions on},
   volume = {30},
   number = {2},
   pages = {328-340},
   abstract = {The minimax approach to the design of systems that are robust with respect to modeling uncertainties is studied using a game theoretic formulation in which the performance functional and the sets of modeling uncertainties and admissible design policies are arbitrary. The existence and characterization of minimax robust solutions that form saddle points are discussed through various methods that take into account several common features of the games encountered in applications. In particular, it is shown that if the performance functional and the uncertainty set are convex then a certain type of regularity condition on the functional is sufficient to ensure that the optimal strategy for a least favorable element of the uncertainty set is minimax robust. The efficacy of the methods proposed for a general game is tested in the problems of matched filtering, Wiener filtering, quadratic detection, and output energy filtering, in which uncertainties in their respective signal and noise models are assumed to exist. These problems are analyzed in a common Hilbert space framework and they serve to point out the advantages and limitations of the proposed techniques.},
   keywords = {Game theory
Minimax optimization
Robustness
Design optimization
Filtering
Hilbert space
Matched filters
Minimax techniques
Noise robustness
Testing
Uncertainty
Wiener filter},
   ISSN = {0018-9448},
   DOI = {10.1109/TIT.1984.1056876},
   url = {http://ieeexplore.ieee.org/ielx5/18/22741/01056876.pdf?tp=&arnumber=1056876&isnumber=22741},
   year = {1984},
   type = {Journal Article}
}

@inproceedings{schulte:1999,
   author = {Schulte, M. J. and Stine, J. E. and Jansen, J. G.},
   title = {Reduced power dissipation through truncated multiplication},
   booktitle = {Low-Power Design, 1999. Proceedings. IEEE Alessandro Volta Memorial Workshop on},
   pages = {61-69},
   abstract = {Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be significantly reduced by a technique known as truncated multiplication. With this technique, the least significant columns of the multiplication matrix are not used. Instead, the carries generated by these columns are estimated. This estimate is added with the most significant columns to produce the rounded product. This paper presents the design and implementation of parallel truncated multipliers. Simulations indicate that truncated parallel multipliers dissipate between 29 and 40 percent less power than standard parallel multipliers for operand sizes of 16 and 32 bits},
   keywords = {digital signal processing chips
low-power electronics
multiplying circuits
parallel architectures
16 bit
32 bit
digital signal processing systems
least significant columns
operand sizes
parallel multipliers
power dissipation
truncated multiplication
word size
Application software
Clocks
Compressors
Concurrent computing
Counting circuits
Delay
Digital signal processing
Frequency
Signal design},
   DOI = {10.1109/LPD.1999.750404},
   url = {http://ieeexplore.ieee.org/ielx4/6066/16204/00750404.pdf?tp=&arnumber=750404&isnumber=16204},
   type = {Conference Proceedings},
  year = {1999}
}

@article{martin:1971,
   author = {Martin, R. and Schwartz, S. C.},
   title = {Robust detection of a known signal in nearly Gaussian noise},
   journal = {Information Theory, IEEE Transactions on},
   volume = {17},
   number = {1},
   pages = {50-56},
   abstract = {A detector that is not nonparametric, but that nevertheless performs well over a broad class of noise distributions is termed a robust detector. One possible way to obtain a certain degree of robustness or stability is to look for a min-max solution. For the problem of detecting a signal of known form in additive, nearly Gaussian noise, the solution to the min-max problem is obtained when the signal amplitude is known and the nearly Gaussian noise is specified by a mixture model. The solution takes the form of a correlator-limiter detector. For a constant signal, the correlator-limiter detector reduces to a limiter detector, which is shown to be robust in terms of power and false alarm. By adding a symmetry constraint to the nearly normal noise and formulating the problem as one of local detection, the limiter-correlator is obtained as the local min-max solution. The limiter-correlator is shown to be robust in terms of asymptotic relative efficiency (ARE). For a pulse train of unknown phase, a limiter-envelope sum detector is also shown to be robust in terms of ARE.},
   keywords = {Correlators
Limiting
Minimax detection
Nonparametric detection
Additive noise
Detectors
Distribution functions
Gaussian noise
Minimax techniques
Noise robustness
Phase detection
Robust stability
Signal detection
Testing},
   ISSN = {0018-9448},
   DOI = {10.1109/TIT.1971.1054590},
   url = {http://ieeexplore.ieee.org/ielx5/18/22655/01054590.pdf?tp=&arnumber=1054590&isnumber=22655},
   year = {1971},
   type = {Journal Article}
}

@article{elsawy:1977,
   author = {El-Sawy, A. and Vandelinde, V. D.},
   title = {Robust detection of known signals},
   journal = {Information Theory, IEEE Transactions on},
   volume = {23},
   number = {6},
   pages = {722-727},
   abstract = {The problem of detection of known signals in additive noise is solved under the assumption that the unknown noise density is a member of some known family of symmetric densities. A general approach to the design of receivers that are asymptotically most robust is established. As an example, a detector is derived by applying the procedure to the special case obtained when the noise density family is defined by<tex>F=left{f left| int^{a}_{-a} f(x) dx = p, f mbox{symmetric} right}.</tex>Simulation results showing the detector's performance for small sample sizes are provided.},
   keywords = {Signal detection
Additive noise
Contamination
Density functional theory
Detectors
Estimation theory
Gaussian noise
Helium
Noise robustness
Testing},
   ISSN = {0018-9448},
   DOI = {10.1109/TIT.1977.1055790},
   url = {http://ieeexplore.ieee.org/ielx5/18/22699/01055790.pdf?tp=&arnumber=1055790&isnumber=22699},
   year = {1977},
   type = {Journal Article}
}

@article{bath:1982,
   author = {Bath, W. and Vandelinde, V. D.},
   title = {Robust memoryless quantization for minimum signal distortion},
   journal = {Information Theory, IEEE Transactions on},
   volume = {28},
   number = {2},
   pages = {296-306},
   abstract = {Robust quantizers are designed for situations where there is only an incomplete statistical description of the quantizer input. The goal of the design is to closely approximate quantizer inputs by quantizer outputs without using more than a specified number of quantization levels. The exact probability distribution of the input is unknown, but this distribution is known to belong to some set<tex>C</tex>. The primary, set<tex>C</tex>considered is the set of all unimodal probability distributions which satisfy generalized moment constraint (e.g., mean-square value less than or equal to a constant). A quantizer is derived which minimizes over all quantizers the maximum distortion over all distributions in<tex>C</tex>. This robust quantizer guarantees a significanfiy lower worst case distortion than the classical Gaussian-optimal quantizer, while performing nearly as well as the Gaussian-optimal quantizer when the input is, in fact, Gaussian.},
   keywords = {Quantization (signal)
Signal quantization
Communication system control
Control systems
Distortion measurement
Gaussian distribution
Minimax techniques
Noise robustness
Physics
Probability distribution
Quantization
Signal design},
   ISSN = {0018-9448},
   DOI = {10.1109/TIT.1982.1056475},
   url = {http://ieeexplore.ieee.org/ielx5/18/22725/01056475.pdf?tp=&arnumber=1056475&isnumber=22725},
   year = {1982},
   type = {Journal Article}
}

@article{kassam:1983,
   author = {Kassam, S. and Poor, H. V.},
   title = {Robust signal processing for communication systems},
   journal = {Communications Magazine, IEEE},
   volume = {21},
   number = {1},
   pages = {20-28},
   abstract = {Not Available},
   keywords = {Game theory
Minimax optimization
Robust methods
Signal detection
Signal processing
Additive noise
Minimax techniques
Power system modeling
Robustness
Signal design
Signal to noise ratio
Statistics},
   ISSN = {0163-6804},
   DOI = {10.1109/MCOM.1983.1091322},
   url = {http://ieeexplore.ieee.org/ielx5/35/23778/01091322.pdf?tp=&arnumber=1091322&isnumber=23778},
   year = {1983},
   type = {Journal Article}
}

@article{kassam:1985,
   author = {Kassam, S. A. and Poor, H. V.},
   title = {Robust techniques for signal processing: A survey},
   journal = {Proceedings of the IEEE},
   volume = {73},
   number = {3},
   pages = {433-481},
   abstract = {In recent years there has been much interest in robustness issues in general and in robust signal processing schemes in particular. Robust schemes are useful in situations where imprecise a priori knowledge of input characteristics makes the sensitivity of performance to deviations from assumed conditions an important factor in the design of good signal processing schemes. In this survey we discuss the minimax approach for the design of robust methods for signal processing. This has proven to be a very useful approach because it leads to constructive procedures for designing robust schemes. Our emphasis is on the contributions which have been made in robust signal processing, although key results of other robust statistical procedures are also considered. Most of the results we survey have been obtained in the past fifteen years, although some interesting earlier ideas for minimax signal processing are also mentioned. This survey is organized into five main parts, which deal separately with robust linear filters for signal estimation, robust linear filters for signal detection and related applications, nonlinear methods for robust signal detection, nonlinear methods for robust estimation, and robust data quantization. The interrelationships among many of these results are also discussed in the survey.},
   keywords = {Additive noise
Gaussian noise
Minimax techniques
Nonlinear filters
Radar signal processing
Robustness
Signal design
Signal detection
Signal processing
Working environment noise},
   ISSN = {0018-9219},
   DOI = {10.1109/PROC.1985.13167},
   url = {http://ieeexplore.ieee.org/ielx5/5/31347/01457435.pdf?tp=&arnumber=1457435&isnumber=31347},
   year = {1985},
   type = {Journal Article}
}

@article{huber:1965,
   author = {Huber, Peter J.},
   title = {A Robust Version of the Probability Ratio Test},
   pages = {1753-1758},
   abstract = {A statistical procedure is called robust, if its performance is insensitive to small deviations of the actual situation from the idealized theoretical model. In particular, a robust procedure should be insensitive to the presence of a few "bad" observations; that is, a small minority of the observations should never be able to override the evidence of the majority. (But at the same time the discordant minority might be a prime source of information for improving the theoretical model!) The classical probability ratio test is not robust in this sense: a single factor $p_1(x_j)/p_0(x_j)$ equal (or almost equal) to 0 or $\infty$ may upset the test statistic $T(x) = \prod^n_1 p_1(x_j)/p_0(x_j)$. This leads to the conjecture that appropriate robust substitutes to both fixed sample size and sequential probability ratio tests might be obtained by censoring the single factors at some fixed numbers $c' < c''$. Thus, one would replace the test statistic by $T'(x) = \prod^n_1 \pi(x_j)$, where $\pi(x_j) = \max (c', \min (c'', p_1(x_j)/p_0(x_j)))$. The problem of robustly testing a simple hypothesis $P_0$ against a simple alternative $P_1$ may be formalized by assuming that the true underlying distribution lies in some neighborhood of either of the idealized model distributions $P_0$ or $P_1$. The present paper exhibits two different types of such neighborhoods for which the above mentioned test, to be called censored probability ratio test, is most robust in a well defined minimax sense. The problem solved here originated through the earlier paper Huber (1964), over the question how to test hypotheses about the mean of contaminated normal distributions.},
   ISSN = {0003-4851},
   DOI = {10.1214/aoms/1177699803},
   url = {http://projecteuclid.org/euclid.aoms/1177699803},
   year = {1965},
   type = {Journal Article}
}



@article{petra:2010,
   author = {Petra, N. and De Caro, D. and Garofalo, V. and Napoli, E. and Strollo, A. G. M.},
   title = {Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error},
   journal = {Circuits and Systems I: Regular Papers, IEEE Transactions on},
   volume = {57},
   number = {6},
   pages = {1312-1325},
   abstract = {Truncated multipliers compute the n most-significant bits of the n &#x00D7; n bits product. This paper focuses on variable-correction truncated multipliers, where some partial-products are discarded, to reduce complexity, and a suitable compensation function is added to partly compensate the introduced error. The optimal compensation function, that minimizes the mean square error, is obtained in this paper in closed-form for the first time. A sub optimal compensation function, best suited for hardware implementation, is introduced. Efficient multipliers implementation based on sub-optimal function is discussed. Proposed truncated multipliers are extensively compared with previously proposed circuits. Experimental results, for a 0.18 &#x03BC;m technology, are also presented.},
   keywords = {error compensation
least mean squares methods
multiplying circuits
error compensation function
minimum mean square error
size 0.18 mum
truncated binary multipliers
variable-correction truncated multipliers
Multiplication
digital arithmetic
error analysis
least mean square method
truncated multipliers},
   ISSN = {1549-8328},
   DOI = {10.1109/TCSI.2009.2033536},
   url = {http://ieeexplore.ieee.org/ielx5/8919/5482395/05356214.pdf?tp=&arnumber=5356214&isnumber=5482395},
   year = {2010},
   type = {Journal Article}
}

@inproceedings{swartzlander:1999,
   author = {Swartzlander, E. E.},
   title = {Truncated multiplication with approximate rounding},
   booktitle = {Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on},
   volume = {2},
   pages = {1480-1483 vol.2},
   year = {1999},
   abstract = {In many signal processing applications it is desirable to maintain constant word size through the basic arithmetic operations of add, subtract, multiply and divide. Of these operations, multiply is the biggest concern as multiplying two n-bit data yields a 2n-bit product. Forming the full product and rounding it to the desired precision is mathematically attractive, but the complexity is high. Forming a portion of the bit product matrix would reduce the complexity, but this incurs potentially large errors. A compromise approach has been developed that represents a reasonable (in many applications) compromise. The complexity is slightly above that of a truncated bit product multiplier, but the accuracy is close to that of a rounded full precision multiplier.},
   keywords = {computational complexity
digital arithmetic
signal processing
approximate rounding
arithmetic operations
bit product matrix
complexity reduction
rounded full precision multiplier
signal processing applications
truncated bit product multiplier
truncated multiplication
Added delay
Adders
Application software
Circuits
Hardware},
   ISBN = {1058-6393},
   DOI = {10.1109/ACSSC.1999.831996},
   url = {http://ieeexplore.ieee.org/ielx5/6676/17893/00831996.pdf?tp=&arnumber=831996&isnumber=17893},
   type = {Conference Proceedings}
}

@inproceedings{schulte:1993,
   author = {Schulte, M. J. and Swartzlander, E. E.},
   title = {Truncated multiplication with correction constant [for DSP]},
   booktitle = {VLSI Signal Processing, VI, 1993., [Workshop on]},
   pages = {388-396},
  year = {1993},
   keywords = {VLSI
digital arithmetic
error correction
matrix multiplication
multiplying circuits
systolic arrays
VLSI implementations
average error
correction constant
digital signal processing
maximum error
mean square error
parallel multiplication
reduced hardware requirements
rounded output multipliers
truncated multiplication
Concurrent computing
Equations
Hardware
Limiting
Mean square error methods
Roundoff errors
Signal processing
Very large scale integration},
   DOI = {10.1109/VLSISP.1993.404467},
   url = {http://ieeexplore.ieee.org/ielx2/3196/9097/00404467.pdf?tp=&arnumber=404467&isnumber=9097},
   type = {Conference Proceedings}
}

@inproceedings{hyuk:2006,
   author = {Hyuk, Park and Swartzlander, E. E.},
   title = {Truncated Multiplication with Symmetric Correction},
   booktitle = {Signals, Systems and Computers, 2006. ACSSC '06. Fortieth Asilomar Conference on},
   pages = {931-934},
   year = {2006},
   abstract = {In the design of digital signal processing systems, where single-precision results are required, the power dissipation and area of parallel multipliers can be significantly reduced by truncating the less significant columns and compensating to produce an approximate rounded product. This paper provides a new method for truncated multiplication, which yields less errors than the previous methods with only slightly more complexity by a specialized counter. An error pattern is exhaustively analyzed with all possible inputs to evaluate the errors by the proposed correction method. Error and hardware comparisons of the previous methods and the proposed correction method are presented. The proposed method is applied to both unsigned and two's complement multipliers.},
   keywords = {digital signal processing chips
integrated circuit design
low-power electronics
multiplying circuits
approximate rounded product
digital signal processing system design
parallel multiplier
power dissipation
symmetric correction method
truncated multiplication
Counting circuits
Digital signal processing
Energy consumption
Error analysis
Error correction
Hardware
Logic
Pattern analysis
Signal design},
   ISBN = {1058-6393},
   DOI = {10.1109/ACSSC.2006.354887},
   url = {http://ieeexplore.ieee.org/ielx5/4176490/4176491/04176697.pdf?tp=&arnumber=4176697&isnumber=4176491},
   type = {Conference Proceedings}
}

@inproceedings{walters:2011,
   author = {Walters, E. G. and Schulte, M. J.},
   title = {Truncated-matrix multipliers with coefficient shifting},
   booktitle = {Signals, Systems and Computers (ASILOMAR), 2011 Conference Record of the Forty Fifth Asilomar Conference on},
   pages = {176-180},
   year = {2011},
   abstract = {Truncated-matrix multipliers offer significant reductions in area, power, and delay, at the expense of increased computational error. These tradeoffs make them an attractive choice for many signal processing systems such as FIR filters. This paper presents a method for shifting coefficients that significantly reduces the error in systems that use truncated-matrix multipliers. This method allows further reductions in area, power, and delay while maintaining the overall accuracy of the system.},
   keywords = {FIR filters
matrix algebra
signal processing
coefficient shifting
computational error
shifting coefficients
signal processing systems
significant reductions
truncated matrix multipliers
Computers
Delay
Digital signal processing
Finite impulse response filter
Frequency response
Signal to noise ratio},
   ISBN = {1058-6393},
   DOI = {10.1109/ACSSC.2011.6189979},
   url = {http://ieeexplore.ieee.org/ielx5/6185739/6189941/06189979.pdf?tp=&arnumber=6189979&isnumber=6189941},
   type = {Conference Proceedings}
}

@inproceedings{wires:2000,
   author = {Wires, K. E. and Schulte, M. J. and Stine, J. E.},
   title = {Variable-correction truncated floating point multipliers},
   booktitle = {Signals, Systems and Computers, 2000. Conference Record of the Thirty-Fourth Asilomar Conference on},
   volume = {2},
   pages = {1344-1348 vol.2},
   year = {2000},
   abstract = {About half the hardware for floating point multipliers is needed only to guarantee correctly rounded results. For multimedia, graphics, and DSP systems, a significant reduction in area, delay, and power can be achieved by producing results that are not correctly rounded. This paper presents an efficient method for designing variable-correction truncated floating point multipliers that produce results with a maximum error of less than one unit in the last place. With this method, several of the less significant columns of the significand multiplier are eliminated and the rounding logic for floating point multiplication is simplified.},
   keywords = {floating point arithmetic
logic circuits
multiplying circuits
normalization logic
rounding logic
significand multiplier
variable-correction truncated floating point multipliers
Delay
Digital signal processing
Floating-point arithmetic
Graphics
H infinity control
Hardware
Power engineering and energy
Power engineering computing
USA Councils
Wires},
   ISBN = {1058-6393},
   DOI = {10.1109/ACSSC.2000.911211},
   url = {http://ieeexplore.ieee.org/ielx5/7268/19639/00911211.pdf?tp=&arnumber=911211&isnumber=19639},
   type = {Conference Proceedings}
}

@inproceedings{stine:2003,
   author = {Stine, J. E. and Duverne, O. M.},
   title = {Variations on truncated multiplication},
   booktitle = {Digital System Design, 2003. Proceedings. Euromicro Symposium on},
   pages = {112-119},
   year = {2003},
   abstract = {Truncated multiplication can be used to significantly reduce the power dissipation for applications that do not require correctly-rounded results. This paper presents an efficient method for truncated multiplication called hybrid-correction truncation that utilizes the advantages of two previous methods to obtain lower average and maximum absolute error. Comparisons are presented contrasting power, area, and delay for all three methods compared to standard parallel multipliers. Estimates indicate that hybrid truncated multipliers dissipate slightly less power and consume slightly less area than previous methods for truncated multiplication. In addition, utilization of the hybrid truncation method can provide a method for altering the implementation within certain limits to meet a given precision.},
   keywords = {digital arithmetic
multiplying circuits
hybrid-correction truncation
lower average
maximum absolute error
power dissipation
truncated multiplication
Application software
Clocks
Computer architecture
Delay
Digital signal processing
Hardware
Laboratories
Very large scale integration},
   DOI = {10.1109/DSD.2003.1231908},
   url = {http://ieeexplore.ieee.org/ielx5/8715/27588/01231908.pdf?tp=&arnumber=1231908&isnumber=27588},
   type = {Conference Proceedings}
}
@book{poor1994introduction,
  title={An introduction to signal detection and estimation},
  author={Poor, H Vincent},
  year={1994},
  publisher={Springer}
}
@Manual{tuan2014,
author = {Nguyen, T.},
title = {Truncated Multipliers Version 1},
year = {2014},
url = {https://code.google.com/p/trunc-mult-aio/},
note = {Available at {http://trunc-mult-aio.googlecode.com/svn/trunk/}}
}
